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fm24cl64b 64-kbit (8 k 8) serial (i 2 c) f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-84458 rev. *d revised february 19, 2014 256-kbit (32 k 8) serial (i 2 c) nvsram features 64-kbit ferroelectric random access memory (f-ram) logically organized as 8 k 8 ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endurance table) ? nodelay? writes ? advanced high-reliability ferroelectric process fast 2-wire serial interface (i 2 c) ? up to 1-mhz frequency ? direct hardware replacement for serial (i 2 c) eeprom ? supports legacy timings for 100 khz and 400 khz low power consumption ? 100 ? a (typ) active current at 100 khz ? 3 ? a (typ) standby current voltage operation: v dd = 2.7 v to 3.65 v industrial temperature: ?40 ? c to +85 ? c packages ? 8-pin small outline integrated circuit (soic) package ? 8-pin thin dual flat no leads (tdfn) package restriction of hazardous substances (rohs) compliant functional overview the fm24cl64b is a 64-kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by eeprom and other nonvolatile memories. unlike eeprom, the fm24cl64b perf orms write operations at bus speed. no write delays are incurred. data is written to the memory array immediately af ter each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial write endurance co mpared with other nonvolatile memories. also, f-ram exhibits much lower power during writes than eeprom since write operations do not require an internally elevated power supply voltage for write circuits. the fm24cl64b is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom. these capabilities make the fm24cl64b ideal for nonvolatile memory applications, requirin g frequent or rapid writes. examples range from data loggin g, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the fm24cl64b provides substantial benefits to users of serial (i 2 c) eeprom as a hardware drop-in replacement. the device specifications are guaranteed ov er an industrial temperature range of ?40 ? c to +85 ? c. logic block diagram address latch 8 k x 8 f-ram array data latch 8 sda counter serial to parallel converter control logic scl wp a2-a0 13 8
fm24cl64b document number: 001-84458 rev. *d page 2 of 19 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 overview ............................................................................ 4 memory architecture ........................................................ 4 i2c interface ...................................................................... 4 stop condition (p) ..................................................... 4 start condition (s) ................................................... 4 data/address transfer ................................................ 5 acknowledge / no-acknowledge ................................. 5 slave device address ......... ........................................ 6 addressing overview .......... ........................................ 6 data transfer .............................................................. 6 memory operation ............................................................ 6 write operation ........................................................... 6 read operation ........................................................... 7 endurance ......................................................................... 8 maximum ratings ............................................................. 9 operating range ............................................................... 9 dc electrical characteristics .......................................... 9 data retention and endurance ..................................... 10 capacitance .................................................................... 10 thermal resistance ........................................................ 10 ac test loads and waveforms ..................................... 11 ac test conditions ........................................................ 11 ac switching characteristics ....................................... 12 power cycle timing ....................................................... 13 ordering information ...................................................... 14 ordering code definitions ..... .................................... 14 package diagrams .......................................................... 15 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc? solutions ...................................................... 19 cypress developer community ................................. 19 technical support ................. .................................... 19
fm24cl64b document number: 001-84458 rev. *d page 3 of 19 pinouts figure 1. 8-pin soic pinout figure 2. 8-pin tdfn pinout wp scl 1 2 3 4 5 a0 8 7 6 v dd sda a1 top view not to scale v ss a2 a1 a0 v ss a2 sda v dd scl wp 1 2 45 6 7 8 3 o pad exposed top view not to scale pin definitions pin name i/o type description a2-a0 input device select address 2-0 . these pins are used to select one of up to 8 devices of the same type on the same i 2 c bus. to select the device, the address va lue on the three pins must match the corre- sponding bits contained in the slave address. the address pins are pulled down internally. sda input/output serial data/address . this is a bi-directional pin for the i 2 c interface. it is open-drain and is intended to be wire-and'd with other devices on the i 2 c bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. an external pull-up resistor is required. scl input serial clock . the serial clock pin for the i 2 c interface. data is clocked out of the device on the falling edge, and into the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. wp input write protect . when tied to v dd , addresses in the entire memory map will be write-protected. when wp is connected to ground, all addresses are wr ite enabled. this pin is pulled down internally. v ss power supply ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device. exposed pad no connect the exposed pad on the botto m of 8-pin tdfn package is not connected to the die. the exposed pad should be left floating.
fm24cl64b document number: 001-84458 rev. *d page 4 of 19 overview the fm24cl64b is a serial f-ram memory. the memory array is logically organized as 8,192 8 bits and is accessed using an industry-standard i 2 c interface. the functional operation of the f-ram is similar to serial (i 2 c) eeprom. the major difference between the fm24cl64b and a serial (i 2 c) eeprom with the same pinout is the f-ram's superior write performance, high endurance, and low power consumption. memory architecture when accessing the fm24cl64b, the user addresses 8k locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the i 2 c protocol, which includes a slave address (to distinguish other non-memory devices) and a two-byte address. the upper 3 bits of the address range are 'don't care' values. the complete address of 13 bits specifies each byte address uniquely. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the i 2 c bus. unlike a serial (i 2 c) eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted into the device, a write operation is complete. this is explained in more detail in the interface section. i 2 c interface the fm24cl64b employs a bi-directional i 2 c bus protocol using few pins or board space. figure 3 illustrates a typical system configuration using the fm24cl64b in a microcontroller-based system. the industry standard i 2 c bus is familiar to many users but is described in this section. by convention, any dev ice that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling th e bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm24cl64b is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 4 and figure 5 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electr ical specifications section. stop condition (p) a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm24cl64b should end with a stop condition. if an operation is in progress when a st op is asserted, the operation will be aborted. the master must have control of sda in order to assert a stop condition. start condition (s) a start condition is indicated when the bus master drives sda from high to low while the sc l signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm24cl64b for a new operation. if during operation the power supply drops below the specified v dd minimum, the system should issue a start condition prior to performing another operation. figure 3. system configuration using serial (i 2 c) nvsram sda scl dd 0 a 0 a 0 a a1 a1 a1 l c s l c s l c s sda a d s a d s p w p w p w #0 #1 #7 a2 a2 a2 microcontroller v dd v dd v r pmin = (v dd - v ol max) / i ol r pmax = t r / (0.8473 * c b )
fm24cl64b document number: 001-84458 rev. *d page 5 of 19 data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the three conditions described above, the sda signal should not change while scl is high. acknowledge / no-acknowledge the acknowledge takes place after the 8th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does no t drive sda low, the condition is a no-acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fa ils. in this case, the no-acknowledge ceases the current operation so that the device can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the fm24cl64b will continue to place data onto the bus as long as the receiver sends acknowledge s (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm24cl64b to attempt to drive the bus on the next clock while the master is sending a new command such as stop. figure 4. start and stop conditions full pagewidth sda scl p stop condition sda scl s start condition figure 5 data transfer on the i 2 c bus handbook, full pagewidth s or p sda s p scl stop or start condition s start condition 2 3 4 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from slave byte complete acknowledgement signal from receiver 1 figure 6 acknowledge on the i 2 c bus handbook, full pagewidth s start condition 9 8 2 1 clock pulse for acknowledgement no acknowledge acknowledge data output by master data output by slave scl from master
fm24cl64b document number: 001-84458 rev. *d page 6 of 19 slave device address the first byte that the fm24cl64b expects after a start condition is the slave address. as shown in figure 7 , the slave address contains the device type or slave id, the device select address bits, and a bit that specif ies if the transaction is a read or a write. bits 7-4 are the device type (slave id) and should be set to 1010b for the fm24cl64b. these bits allow other function types to reside on the i 2 c bus within an identical address range. bits 3-1 are the device select address bits . they must match the corre- sponding value on the external address pins to select the device. up to eight fm24cl64b devices can reside on the same i 2 c bus by assigning a different address to each. bit 0 is the read/write bit (r/w ). r/w = ?1? indicates a read operation and r/w = ?0? indicates a write operation. addressing overview after the fm24cl64b (as receiver) acknowledges the slave address, the master can plac e the memory address on the bus for a write operation. the address requires two bytes. the complete 13-bit address is latched internally. each access causes the latched address value to be incremented automati- cally. the current address is the value that is held in the latch; either a newly written value or the address following the last access. the current address will be held for as long as power remains or until a new value is written. reads always use the current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm24cl64b increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (1fffh) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. data transfer after the address bytes have been transmitted, data transfer between the bus master and the fm24cl64b can begin. for a read operation the fm24cl64b will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occurs, the fm24cl64b will transfer the next sequential byte. if the acknowledge is not sent, the fm24cl64b will end the read operation. for a write operation, the fm24cl64b will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm24cl64b is designed to operate in a manner very similar to other i 2 c interface memory products. the major differences result from the higher perfo rmance write capability of f-ram technology. these improvements result in some differences between the fm24cl64b and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the lsb of the slave address (r/w bit) to a '0'. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condit ion. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from 1fffh to 0000h. unlike other nonvolatile memory technologies, there is no effective write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through th e bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or writ e can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8th data bit. the fm24cl64b uses no page buffering. the memory array can be writ e-protected using the wp pin. setting the wp pin to a high condition (v dd ) will write-protect all addresses. the fm24cl64b will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if wr ites are attempted to these addresses. setting wp to a low state (v ss ) will disable the write protect. wp is pulled down internally. figure 8 and figure 9 below illustrate a single-byte and multiple-byte write cycles. figure 7. memory slave device address handbook, halfpage r/w lsb msb slave id 10 1 0 a2 a0 a1 device select figure 8 single-byte write s a slave address 0 address msb a data byte a p by master by f-ram start address & data stop acknowledge address lsb a
fm24cl64b document number: 001-84458 rev. *d page 7 of 19 read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the fm24cl64b uses the internal address latch to supply the address. in a selective read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the fm24cl64b uses an internal latch to supply the address for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operation. the syst em reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a '1'. this indicates that a read operation is requested. after receiving the complete slave address, the fm24cl64b will begin shifting out data from the current address on the next clock. the current address is the value held in the internal address latch. beginning with the current addres s, the bus master can read any number of bytes. thus, a seq uential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. note each time the bus master acknowledges a byte, this indicates that the fm24cl64b should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the fm24cl64b attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clo ck cycle. this is illustrated in the diagrams below. this is preferred. 2. the bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. 3. the bus master issues a stop in the 9th clock cycle. 4. the bus master issues a start in the 9th clock cycle. if the internal address reache s 1fffh, it will wrap around to 0000h on the next read cycle. figure 10 and figure 11 below show the proper operation for current address reads. figure 9. multi-byte write s a slave address 0 address msb a data byte a p by master by f-ram start address & data stop acknowledge address lsb a data byte a figure 10. current address read s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data figure 11. sequential read s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data data byte a acknowledge
fm24cl64b document number: 001-84458 rev. *d page 8 of 19 selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb (r/w ) set to 0. this specifies a write operation. according to the writ e protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm24cl64b acknowledges the address, the bus master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a '1'. the operation is now a current address read. endurance the fm24c64b internally operates with a read and restore mechanism. therefore, endurance cycles are applied for each read or write cycle. the memory architecture is based on an array of rows and columns. each read or write access causes an endurance cycle for an entire row. in the fm24c64b, a row is 64 bits wide. every 8-byte boun dary marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows. regardless, fram read and write endurance is effectively unlimited at the 1mhz i 2 c speed. even at 3000 accesses per second to the same segment, 10 years time will elapse before 1 trillion endurance cycles occur. figure 12. selective (random) read s a slave address 1 data byte 1 p by master by f-ram start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a
fm24cl64b document number: 001-84458 rev. *d page 9 of 19 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ? c maximum junction temperature ................................... 95 ? c supply voltage on v dd relative to v ss .........?1.0 v to +5.0 v input voltage .......... ?1.0 v to + 5.0 v and v in < v dd + 1.0 v dc voltage applied to outputs in high-z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (10 seconds) ....................................... +260 ? c electrostatic discharge voltage human body model (aec-q100-002 rev. e) ..................... 4 kv charged device model (aec-q100-011 rev. b) ............. 1.25 kv machine model (aec-q100-003 rev. e) ............................ 300 v latch-up current .................................................... > 140 ma * exception: the "v in < v dd + 1.0 v" restriction does not apply to the scl and sda inputs. operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 2.7 v to 3.65 v dc electrical characteristics over the operating range parameter description test conditions min typ [1] max unit v dd power supply 2.7 3.3 3.65 v i dd average v dd current scl toggling between v dd ? 0.3 v and v ss , other inputs v ss or v dd ? 0.3 v. f scl = 100 khz ? ? 100 ? a f scl = 400 khz ? ? 170 ? a f scl = 1 mhz ? ? 300 ? a i sb standby current scl = sda = v dd . all other inputs v ss or v dd . stop command issued. ?36 ? a i li input leakage current (except wp and a2-a0) v ss < v in < v dd ?1 ? +1 ? a input leakage current (for wp and a2-a0) v ss < v in < v dd ?1 ? +100 ? a i lo output leakage current v ss < v in < v dd ?1 ? +1 ? a v ih input high voltage 0.7 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.3 v dd v v ol output low voltage i ol = 3 ma ? ? 0.4 v r in [2] input resistance (wp, a2-a0) for v in = v il (max) 40 ? ? k ? for v in = v ih (min) 1??m ? v hys [3] input hysteresis 0.05 v dd ??v notes 1. typical values are at 25 c, v dd = v dd (typ). not 100% tested. 2. the input pull-down circuit is strong (40 k ? ) when the input voltage is below v il and weak (1 m ? ) when the input voltage is above v ih . 3. this parameter is guaranteed by design and is not tested.
fm24cl64b document number: 001-84458 rev. *d page 10 of 19 data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c10?years t a = 75 ? c38? t a = 65 ? c 151 ? nv c endurance over operating temperature 10 14 ? cycles capacitance parameter [4] description test conditions max unit c o output pin capacitance (sda) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter [4] description test conditions 8-pin soic 8-pin tdfn unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 147 28 ? c/w ? jc thermal resistance (junction to case) 47 30 ? c/w note 4. this parameter is periodically sampled and not 100% tested.
fm24cl64b document number: 001-84458 rev. *d page 11 of 19 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times .................................................10 ns input and output timing reference levels ................0.5 v dd output load capacitance ............................................ 100 pf ac test loads and waveforms figure 13. ac test loads and waveforms 3.6 v output 100 pf 1.1 k ?
fm24cl64b document number: 001-84458 rev. *d page 12 of 19 ac switching characteristics over the operating range parameter [5] alt. parameter description min max min max min max unit f scl [6] scl clock frequency ? 0.1 ? 0.4 ? 1.0 mhz t su; sta start condition setup for repeated start 4.7 ? 0.6 ? 0.25 ? ? s t hd;sta start condition hold time 4.0 ? 0.6 ? 0.25 ? ? s t low clock low period 4.7 ? 1.3 ? 0.6 ? ? s t high clock high period 4.0?0.6?0.4? ? s t su;dat t su;data data in setup 250 ? 100 ? 100 ? ns t hd;dat t hd;data data in hold 0 ? 0 ? 0 ? ns t dh data output hold (from scl @ v il )0?0?0?ns t r [7] t r input rise time ? 1000 ? 300 ? 300 ns t f [7] t f input fall time ? 300 ? 300 ? 100 ns t su;sto stop condition setup 4.0 ? 0.6 ? 0.25 ? ? s t aa t vd;data scl low to sda data out valid ? 3 ? 0.9 ? 0.55 ? s t buf bus free before new transmission 4.7 ? 1.3 ? 0.5 ? ? s t sp noise suppression time constant on scl, sda ? 50 ? 50 ? 50 ns figure 14. read bus timing diagram figure 15. write bus timing diagram t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:dat t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda notes 5. test conditions assume signal transition time of 10 ns or less, timing reference levels of v dd /2, input pulse levels of 0 to v dd (typ), and output loading of the specified i ol and load capacitance shown in figure 13 . 6. the speed-related specifications are guar anteed characteristic points along a continuous curve of operation from dc to f scl (max). 7. these parameters are guaranteed by design and are not tested.
fm24cl64b document number: 001-84458 rev. *d page 13 of 19 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (start condition) 1 ? ms t pd last access (stop condition) to power-down (v dd (min)) 0 ? s t vr [8, 9] v dd power-up ramp rate 30 ? s/v t vf [8, 9] v dd power-down ramp rate 30 ? s/v figure 16. power cycle timing sda ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) i c start 2 i c stop 2 note 8. slope measured at any point on the v dd waveform. 9. guaranteed by design.
fm24cl64b document number: 001-84458 rev. *d page 14 of 19 ordering information ordering code package diagram package type operating range fm24cl64b-g 001-85066 8-pin soic industrial fm24cl64b-gtr all these parts are pb-free. contact your local cypre ss sales representative for availability of these parts. ordering code definitions option: blank = standard; t = tape and reel package type: g = 8-pin soic die revision = b density: 64 = 64-kbit voltage: cl = 2.7 v to 3.65 v i 2 c f-ram cypress 24 fm cl 64 b g tr -
fm24cl64b document number: 001-84458 rev. *d page 15 of 19 package diagrams figure 17. 8-pin soic (150 mils) package outline, 51-85066 51-85066 *f 51-85066 *f
fm24cl64b document number: 001-84458 rev. *d page 16 of 19 figure 18. 8-pin dfn (4.0 4.5 0.8 mm) package outline, 001-85260 package diagrams (continued) 001-85260 *a
fm24cl64b document number: 001-84458 rev. *d page 17 of 19 acronyms document conventions units of measure acronym description ack acknowledge cmos complementary metal oxide semiconductor eia electronic industries alliance i 2 c inter-integrated circuit i/o input/output jedec joint electron devices engineering council lsb least significant bit msb most significant bit nack no acknowledge rohs restriction of hazardous substances r/w read/write scl serial clock line sda serial data access soic small outline integrated circuit wp write protect tdfn thin dual flat no-lead symbol unit of measure c degree celsius hz hertz kb 1024 bit khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
fm24cl64b document number: 001-84458 rev. *d page 18 of 19 document history page document title: fm24cl64b, 64 -kbit (8 k 8) serial (i 2 c) f-ram document number: 001-84458 rev. ecn no. submission date orig. of change description of change ** 3902082 02/25/2013 gvch new spec *a 3924523 03/07/2013 gvch changed tpu spec value from 10 ms to 1 ms *b 3996669 05/13/2013 gvch added appendix a - errata for fm24cl64b *c 4045469 06/30/2013 gvch all errata items are fixed and the errata is removed. *d 4283420 02/19/2014 gvch converted to cypress standard format updated pinouts - updated figure 2 (added exposed pad details) updated pin definitions - added exposed pad details updated maximum ratings table - removed moisture sensitivity level (msl) - added junction temperature and latch up current added input leakage current (i li ) for wp and a2-a0 updated data retention and endurance table added thermal resistance table removed package marking scheme (top mark) removed ramtron revision history completing sunset review
document number: 001-84458 rev. *d revised february 19, 2014 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. fm24cl64b ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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